A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

This article presents a low power digital controlled oscillator (DCO) with an ultra duty cycle correction (DCC) scheme. The DCO the complementary cross-coupled topology uses controllable tail resistor to improve current efficiency. A robust scheme is introduced replace self-biased inverters save further. proposed implemented in Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. measured phase noise at room temperature −115 dBc/Hz 1 MHz offset dissipation of 210 μμW oscillating frequency 2.12 GHz, and resulin figure-of-merit s −189 dBc/Hz.